Historically, as reported in Assignee's U.S. Pat. No. 5,838,542, when microprocessors were first commercialized, each microprocessor held less than one million transistors, and operated at speeds below 20 MHz. Typically, the microprocessors were either solder mounted onto the motherboards directly or mounted to the motherboards through sockets. They were typically air cooled, and air flow was typically sustained by a system fan. ESD shielding was not much of a concern.
In the pursuing years, the number of transistors packed into each microprocessor, as well as its operating speed have increased dramatically, especially in recent years. Correspondingly, the amount of heat that needs to be dissipated, as well as the sensitivity to ESD during operation, have increased. As a result, most of today's microprocessor based computer systems employ either local fans and/or heat sinks to help ensure that the microprocessors run cool. At the same time, increased attentions have also been given to designing computer system chassis containing the microprocessors to ensure the ESD requirements are met.
One chassis level solution to ESD protection of electronic equipment, as disclosed in U.S. Pat. No. 6,080,930, involves providing an electrically conductive gasket on a grounded shelf of a card cage which receives movable circuit modules. As a module is slid into the card cage to engage module connectors with backplane pins of the card cage, a surface of the module contacts the gasket, thereby discharging any static electricity on the module because the gasket is grounded through connection to the shelf.
U.S. Pat. No. 6,281,433 discloses another example of chassis level ESD protection, in this case, for a network switching apparatus. A face plate of the network switching apparatus is provided with a multi-layered, coextruded structure which combines first and second polymeric material layers. An outer portion of the face plate is formed of the first polymeric material layer to protect the circuit packs within the apparatus from ESD. The first polymeric material has a composition in which an additive is suspended within a polymeric material to give the outer layer a surface resistivity to dissipate static charges that would otherwise potentially damage the network switch. The second polymeric material layer of the structure is conductive to provide electromagnetic interference (EMI) shielding.
Proposed solutions to ESD protection of circuit chips at the package level include providing a Faraday cage-type structure about the circuit chips in the package to shield them from electrostatic discharges. For example, in European Patent Application Publication No. 0 340 959, an electrically conductive gasket is employed between a heat sink and a printed wiring board carrying one or more circuit chips. The gasket electrically connects a conductive coating on the heat sink with a conductive reference plane in the printed circuit board. The conductive coating on the heat sink is provided over an electrically insulating layer applied to the heat sink. The patentees explain that the conductive layer over the insulating layer on the heat sink provides a surface separate from the heat sink for the accumulation of static charges, and thereby provides protection of chips on the board within the package from electrostatic charges.
Assignee's U.S. Pat. No. 5,838,542 discloses a processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage. A metallic plate and a back cover on respective sides of a processor disposed on a processor card, are attached to each other to form a Faraday cage for electro-magnetic shielding EMI emissions from the processor as well as providing ESD protection to the processor card. See also U.S. Pat. No. 6,307,258 wherein an ESD shielding is provided on the outside of the semiconductor die package housing.
These Faraday cage-type solutions to ESD protection at the package level can be relatively costly to manufacture and the outer insulative and conductive coatings required to be applied to the heat sinks or housings in the arrangements are subject to chipping and damage. While chassis level ESD protection has in many applications up to now been sufficient, as microprocessor manufacturers have increased microprocessor speed and shrunk the microprocessor dies in new generation microprocessors, it has been found that the conventional ESD protections in computer systems do not meet legal requirements for immunity from ESD events. For example, a European Community legal requirement for ESD protection of computers states that with a 4 kV contact and 8 kV air discharge ESD pulse at a system level, the computer must continue to work without user intervention. There is a need for an improved method and apparatus for cost effectively increasing the immunity of a semiconductor die, particularly a microprocessor, to ESD events in order to meet this legal requirement.